1. Field of the Invention
The present invention relates to an image processor, and more particularly, to a decoder for HD Photo.
2. Description of the Background Art
Microsoft Corporation has recently proposed HD Photo (or JPEG XR) as a still image file format that offers higher image quality than JPEG while requiring more simple circuit configuration and computation than JPEG 2000.
An encoder for HD Photo includes a color conversion unit, a pre-filter, a frequency transform unit, a quantization unit, a prediction unit and an encoding unit.
The frequency transform unit performs predetermined frequency transform (PCT) on an inputted pixel signal, so as to output frequency data (coefficient data) of highpass, lowpass, and direct current components. One macroblock having 16 pixels in column×16 pixels in row includes 240 sets of frequency data of highpass component, 15 sets of frequency data of lowpass component, and 1 set of frequency data of direct current component for each of luminance Y, chrominance U, and chrominance V.
The quantization unit discards lower (or less significant) data equivalent to the number of digits defined by a quantization coefficient in frequency data of each component inputted from the frequency transform unit, so as to output frequency data after quantization (highpass, lowpass, and direct current component).
The encoding unit splits the frequency data of each component inputted from the prediction unit into upper (or more significant) data (Normal Data) in an upper digit range and lower data (Flex Bits) in a lower digit range. Then the encoding unit performs entropy coding on the Normal Data of each component, and output the same, while outputting the Flex Bits of each component without entropy coding.
A decoder for HD Photo includes a color inverse conversion unit, a post-filter, a frequency inverse transform unit, a dequantization unit, an inverse prediction unit and a decoding unit. The decoder performs processing in reverse order to processing by the encoder, so as to decompress pixel signals from the coded frequency data.
The details of HD Photo are disclosed in, for example, “HD Photo—Photographic Still Image File Format”, [online], 7 Nov. 2006, Microsoft Corporation, [searched in the Internet on 10 Oct. 2007], <URL: http://www.microsoft.com/whdc/xps/hdphotodpk.mspx>. The details of JPEG XR are disclosed in, for example, “Coding of Still Pictures—JBIG JPEG”, [online], 19 Dec. 2007, ISO/IEC JTC 1/SC 29/WG1 N 4392, [searched in the Internet on 4 Mar. 2008], <URL: http://www.itscj.ipsj.orjp/sc29/open/29view/29n9026t.doc> or “Coding of Still Pictures—JBIG JPEG”, [online], 14 Sep. 2008, ISO/IEC JTC 1/SC 29/WG1 N 4739, [searched in the Internet on 17 Sep. 2008], <URL:http://www.itscj.ipsj.orjp/sc29/open/29view/29n9749t.doc>.
FIG. 10 shows a set of frequency data FD in HD Photo. The frequency data FD is split into Normal Data (hereinafter referred to as “ND” for short) in an upper digit range R1 and Flex Bits (herein after referred to as “FB” for short) in a lower digit range R2 by an encoding unit of the encoder. One can set the border between the digit ranges R1 and R2 (i.e., the data length of the Flex Bits) arbitrarily by a predetermined parameter (Model Bit).
FIG. 11 is a flowchart schematically showing the stream of processing in a decoding unit of the decoder for HD Photo. First in a step SP1, decoding of the frequency data of a direct current component (DC component) is performed. When the values of Normal Data of direct current component in a target macroblock are all zero, however, processing in the step SP1 of the macroblock is not performed but skipped.
Next in a step SP2, decoding of the frequency data of a lowpass component (LP component) is performed. Similar to the above, when the values of Normal Data of lowpass components in the target macroblock are all zero, processing in the step SP2 of the macroblock is not performed but skipped.
Next in a step SP3, decoding of the frequency data of highpass component (HP component) is performed. Similar to the above, when the values of Normal Data of highpass component in the target macroblock are all zero, processing in the step SP3 of the macroblock is not performed but skipped.
Next in a step SP4, it is determined whether or not all macroblocks (MB) have been decoded. If there is any macroblock that has not been decoded (i.e., if the result of determination in the step SP4 is “NO”), the target of decoding is updated to a next macroblock in a step SP5, and then the processing in the step SP1 and the following steps is repeated. In contrast, if all macroblocks have been decoded, (i.e., if the result of determination in the step SP4 is “YES”), processing is terminated.
FIG. 12 is a flowchart showing the details of decoding of highpass component (step SP3) in FIG. 11. First in a step SP31, it is determined whether or not a target block includes at least one set of Normal Data having a value that is not zero.
If a set of Normal Data having a value that is not zero is included (i.e., if the result of determination in the step SP31 is “YES”), decoding is performed on 15 sets of Normal Data included in the block in the next step SP32. In contrast, if the values of Normal Data included in the block are all zero (i.e., if the result of determination in the step SP31 is “NO”), processing in the step SP32 of the block is not performed but skipped.
Next in a step SP33, decoding is performed on 15 sets of Flex Bits included in the block.
Next in a step SP34, it is determined whether or not all blocks have been decoded. If there is any block which has not been decoded (i.e., if the result of determination in the step SP34 is “NO”), the target of decoding is updated to a next block in a step SP35, and then processing in the step SP31 and the following steps is repeated.
In contrast, if all blocks have been decoded, (i.e., if the result of determination in the step SP34 is “YES”), it is determined in a next step SP36 whether all of the Y, U, and V components have been decoded. If there is any component which has not been decoded (i.e., if the result of determination in the step SP36 is “NO”), the target of decoding is updated to a next component in a step SP37, and then processing in the step SP31 and the following steps is repeated. In contrast, if all components have been decoded, (i.e., if the result of determination in the step SP36 is “YES”), processing is terminated.
FIG. 13 is a block diagram showing a configuration of a decoding unit 101 of a decoder for HD Photo. The decoding unit 101 includes a barrel shifter 102, an ND decoding unit 103 decoding Normal Data, an FB decoding unit 104 decoding a Flex Bit, and a processing unit 105.
As described above, one macroblock includes 240 sets of frequency data of highpass component, 15 sets of frequency data of lowpass component, and 1 set of frequency data of direct current component. The decoding unit 101 performs decoding on a block including 15 sets of frequency data as a unit region for processing for highpass and lowpass components. Thus the decoding unit 101 processes 16 blocks of highpass component and 1 block of lowpass component for one macroblock.
Decoding of frequency data of highpass component is illustrated below. Referring to FIG. 13, data stream DS of coded frequency data is inputted to the barrel shifter 102.
FIG. 14 shows a part of the data stream DS. In the data stream DS, a group of Normal Data PND0 including 15 sets of Normal Data of a 0th block, a group of Flex Bits PFB0 including 15 sets of Flex Bits of the 0th block, a group of Normal Data PND1 including 15 sets of Normal Data of a 1st block, a group of Flex Bits PFB1 including 15 sets of Flex Bits of the 1st block, . . . , are aligned in this order.
Referring to FIGS. 13 and 14, the barrel shifter 102 first inputs the group of Normal Data PND0 (data D101 in FIG. 13) to the ND decoding unit 103 at time T1. Then the ND decoding unit 103 performs entropy decoding on the group of Normal Data PND0, so as to output decoded data D102 of the group of Normal Data PND0. The decoded data D102 of the group of Normal Data PND0 is inputted to the processing unit 105. When decoding of the group of Normal Data PND0 is completed, the ND decoding unit 103 provides notification regarding the end position of the group of Normal Data PND0 in the data stream DS as data D103 to the barrel shifter 102.
Next the barrel shifter 102 inputs the group of Flex Bits PFB0 (data D104 in FIG. 13) to the FB decoding unit 104 at time T2. Then the barrel shifter 102 refers to the data D103 inputted from the ND decoding unit 103, and sets the position immediately following the end position of the group of Normal Data PND0 in the data stream DS as the leading position of the group of Flex Bits PFB0. The FB decoding unit 104 decodes the group of Flex Bits PFB0, so as to output decoded data D105 of the group of Flex Bits PFB0. The decoded data D105 of the group of Flex Bits PFB0 is inputted to the processing unit 105. When decoding of the group of Flex Bits PFB0 is completed, the FB decoding unit 104 provides notification regarding the end position of the group of Flex Bits PFB0 in the data stream DS as data D106 to the barrel shifter 102.
Next, the barrel shifter 102 inputs the group of Normal Data PND1 (data D101 in FIG. 13) to the ND decoding unit 103 at time T3. Then the barrel shifter 102 refers to the data D106 inputted from the FB decoding unit 104, and sets the position immediately following the end position of the group of Flex Bits PFB0 in the data stream DS as the leading position of the group of Normal Data PND1. The ND decoding unit 103 performs entropy decoding on the group of Normal Data PND1, so as to output decoded data D102 of the group of Normal Data PND1. The decoded data D102 of the group of Normal Data PND1 is inputted to the processing unit 105. When decoding of the group of Normal Data PND1 is completed, the ND decoding unit 103 provides notification regarding the end position of the group of Normal Data PND1 in the data stream DS as data D103 to the barrel shifter 102.
From then on, a group of Flex Bit PFB1, a group of Normal Data PND2, a group of Flex Bit PFB2, . . . , are decoded in order in the same manner as the above. The processing unit 105 performs processing such as sorting and joining of data on the plural sets of decoded data D102 inputted from the ND decoding unit 103 and the plural sets of decoded data D105 inputted from the FB decoding unit 104, and sends out the decoded data after processing to a subsequent processing circuit (inverse prediction unit).
According to an example in FIGS. 13 and 14, decoding of a group of Normal data and decoding of a group of Flex Bits are performed serially. Thus even when decoding of a certain group of Normal Data is completed, start of decoding of a next group of Normal Data needs to be queued until decoding of the group of Flex Bits corresponding to the former group of Normal Data is completed. This queue time in decoding is the bottleneck of a decoder for HD Photo.